*1 Start conditions: Software, external start signal, Pattern match (input only) or start signal from synchronization control connector
*2 Clock conditions: Internal clock, external clock, handshake or clock from synchronization control connector
*3 Stop conditions: Software, external stop signal, specified number of items or stop signal from synchronization control connector
Digital |
|
Number of I/O channels |
32 (32 input - 16 I/O - 32 output), selectable via software |
Signal level |
3.3VDC |
Built-in power |
None |
Input |
|
Input type |
Non-isolated, LVTTL-level (equivalent to 74LV245A), positive logic |
Interrupt |
When used as a general-purpose I/O 4 interrupt input signals are arranged into a single interrupt output signal as INTA. An interrupt is generated at the rising edge (LOW-to-HIGH transition) |
Resistance |
10kΩ |
Output |
|
Output type |
Non-isolated, LVTTL-level (equivalent to 74LV245A), positive logic |
Rating (max) |
3.3VDC 8mA |
Response time |
50nsec |
Data access method |
General-purpose digital I/O or I/O with DMA transfer |
Echo-back function |
Available (when used as a general-purpose output) |
Pattern input |
|
Sampling start trigger |
Software start / external start / pattern match / synchronized control connector |
Sampling stop trigger |
Software stop / external stop / end of transfer / transfer error / specified number of items / synchronized control connector |
Sampling clock |
Sampling timer / external clock input / handshake / synchronized control connector |
Sampling timer |
50ns - 107s, 25ns unit |
Pattern output |
|
Generating start trigger |
Software start / external start / synchronized control connector |
Generating stop trigger |
Software stop / external stop / end of transfer / transfer error / specified number of items / synchronized control connector |
Generating clock |
Output timer / external clock input / handshake / synchronized control connector |
Generating timer |
50ns - 107s, 25ns unit |
Control signals |
|
Signal level |
Non-isolated LVTTL-level |
REQ signal (handshake) |
Negative logic tL = 50ns (min) |
ACK signal (handshake) |
Negative logic tL = 50ns (min) |
External start signal |
Selection of rising / falling edge via software |
External stop signal |
Selection of rising / falling edge via software |
External clock input |
F = 10MHz (max) |
|
DMA transfer |
|
DMA channels |
2 channels (one each for input and output) |
Transfer rate |
80MB / sec |
FIFO |
1K data / ch |
Scatter / Gather function |
64MB / ch |
Synchronized operation |
|
Control output signal |
Selection of output signal via software when specifying a sync master board |
Control input signal |
Selection of sync factor via software when specifying sync slave boards |
Max board count for synchronous operation |
16 (including master board) |
Common section |
|
Wiring distance |
1.5m (dependent upon wiring environment) |
I/O addresses |
Occupies 2 locations any 32 / 64 port boundary |
Power consumption |
3.3V 400mA (max) |
Operating conditions |
0 - 50°C, 10 - 90% RH (no condensation) |
Bus specifications |
PCI Express Base Specification Rev1.0a x1 |
Physical dimensions |
176.41mm (l) x 106.68mm (h) [6.95" x 4.2"] |
Connector |
PCR-E96LMD+ or equivalent |
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